Verilog Communication and Controls Model
MMS develops behavioral Verilog models for complex Analog / Mixed-Signal subsystems. The behavior of complex Analog circuits can be modeled with high accuracy using our EVALę modeling IP, making the models suitable for architecture development and/or system verification. These models use generic Verilog constructs and can be simulated using common Verilog simulators, making them ideal for use in sub-system integration verification tasks and to provide sub-system models to Analog / Mixed-Signal IP customers.
These behavioral models do not use Verilog-A constructs and do not require the use of Verilog-A capable simulators or mixed signal simulators that require Verilog-A simulation capabilities.
Our PLL and SERDES Verilog behavioral models accurately simulate dynamic behavior, such as startup lock times and frequency step lock times, and also accurately simulate jitter transfer so there are no unexpected system issues when your design is fabricated.