Phase Locked Loops (PLLs)
Our designers have more than 10years of experience designing, testing, analyzing and supporting PLLs for use both in ASIC environments as well as for special purposes such as in memory interface and SerDes subsystems.
We focus on a rigorous design and validation methodology to ensure first pass success and can develop PLLs for your custom applications with very short turnaround times.
We have designed PLLs for use in Frequency Synthesis, Clock De-Skew and Clock and Data Recovery Applications. We also have experience designing Spread Spectrum PLLs and All-Digital PLLs.
MMS currently has the following PLL designs available, and can port these designs or develop new PLL designs for your custom applications:
- Our 0.13um Phase Locked Loop IP is under development (70%). Development schedules are influenced by our other commitments. If you have a need that we may be able to fulfill please contact us and we will provide you with more details of development status and consider your needs in our future planning.
We provide detailed Application Notes to assist with implementation of our PLLs in your design. The table of contents for this document can be viewed/downloaded here. We provide the full Application Notes to our business partners under NDA, please contact us for more information.